Description of the Related Art
In recent years, downsizing is demanded for semiconductor devices for use in non-volatile memories of mobile electronics devices such as mobile telephones and IC memory cards. For downsizing, there is a need for packaging technology that the semiconductor chips are efficiently packaged.
FIG. 1 (PRIOR ART) is a cross-sectional view showing a Multi Chip Package (MCP) of Conventional Example 1. Referring to FIG. 1 (PRIOR ART), a semiconductor chip 86 is firmly attached on a relay substrate 80 by using a die attach material 84. A semiconductor chip 90 is firmly attached on the semiconductor chip 86 by using an adhesive 88. Wires 94 are electrically connected to the semiconductor chip 86, and wires 92 are electrically connected to the semiconductor chip 90. The semiconductor chips 86 and 90 are sealed with a sealing resin 96. Solder balls 82 are provided in the relay substrate 80, and the semiconductor chips 86 and 90 are electrically coupled to the outside via the solder balls 82. As described above, the semiconductor chips 86 and 90 are stacked and mounted in MCP.
FIG. 2 (PRIOR ART) is a cross-sectional view of Package on Package (PoP) of Conventional Example 2. Referring to FIG. 2 (PRIOR ART), a semiconductor chip 106 is firmly attached on a relay substrate 100 by using a die attached material 104. The semiconductor chip 106 is electrically connected to the relay substrate 100 by wires 108. The semiconductor chip 106 is sealed with a sealing resin 110. Similarly, a semiconductor chip 126 is firmly attached on a relay substrate 120 by using a die attach material 124. The semiconductor chip 126 is electrically coupled to the substrate 120 by wires 128. The semiconductor chip 126 is sealed with a sealing resin 130. The relay substrate 100 and the relay substrate 120 are electrically coupled by solder balls 122, and solder balls 102 are connected to the relay substrate 100. As described above, in PoP, the packaged semiconductor devices are stacked and mounted by means of bumps.
FIG. 3 (PRIOR ART) is a cross-sectional view of Package in Package (PiP) of Conventional Example 3 disclosed in Japanese Patent Application Publication No. 2003-282814. Referring to FIG. 3 (PRIOR ART), a relay substrate 150 is electrically coupled onto a relay substrate 140 by solder balls 152. A semiconductor chip 156 is firmly attached to the relay substrate 150 by die attach material 154. The semiconductor chip 156 is electrically coupled to the relay substrate 150 by wires 158. The semiconductor chip 156 is sealed with a sealing resin 160. A semiconductor chip 164 is firmly attached to the sealing resin 160 with the use of an adhesive 162. The semiconductor chip 164 is electrically coupled to the relay substrate 140 by using wires 166. The sealing resin 160 and the semiconductor chip 164 are sealed with a sealing resin 168. Solder balls 142 are connected to the relay substrate 140. As described above, in PiP, the packaged semiconductor device is coupled to the relay substrate by the solder balls and the packaged semiconductor device is sealed and mounted with the use of the sealing resin.
In the semiconductor device of Conventional Example 1, in the fabrication process thereof, when the semiconductor chip 86 is mounted on the relay substrate 80, the semiconductor chip 86 cannot be tested until the relay substrate 80 is cut. This is because the conductive pattern formed in the relay substrate 80 is connected to the relay substrates 80 of adjacent semiconductor chips. The conductive pattern is connected to adjacent relay substrates 80 so that current is flown through such connected conductive pattern at the time of forming the conductive pattern in the electrolytic plating process. Also, the semiconductor chip 86 is not sealed with the sealing resin before the semiconductor chip 90 is mounted. Unless the semiconductor chip 86 is tested, the subsequent fabrication process is performed on a defective semiconductor chip 86, thereby increasing the costs.
In the semiconductor device of Conventional Example 2, the area of the pad is needed to connect the relay substrate 100 and the relay substrate 120 by means of the solder balls 122. In addition, the height of the semiconductor is increased. In this manner, there are disadvantages in downsizing.
In the semiconductor device of Conventional Example 3, there are several tens of microns between the relay substrate 140 and the relay substrate 150. For this reason, when the sealing resin 168 is provided, it is difficult to fill the sealing resin between the relay substrate 140 and the relay substrate 150, and it is likely to result in voids. Since only the solder balls 152 are heat conduction paths from the relay substrate 140 to the relay substrate 150, it takes time to retain the temperature while the wires 166 are being bonded. This increases the costs. The height of the semiconductor also increases. As described, there are disadvantages in downsizing.
In the semiconductor device of Conventional Examples 1 through 3, the sealing resins 96, 130, and 168 are respectively provided only on top surfaces of the relay substrates 80, 120, and 140. Accordingly, in some cases, the sealing resin is peeled off from between the relay substrate and the sealing resin, due to the mechanical stress exerted onto the semiconductor device, temperature change, or moisture change.